Field of the Invention
This invention relates generally to the field of computer processors and software. More particularly, the invention relates to an apparatus and method for efficient register reclamation.
Description of the Related Art
Because the latency of accessing a register for reading/writing is usually less than one cycle, the register in a way is the fastest unit of the memory hierarchy. Typically, the “logical” registers, i.e., the registers exposed by the semantics of the instruction set architecture (ISA), are used by the compiler as sources/destinations for operands as well as for holding temporaries. However, prior to execution of this code on the hardware, the logical registers (LRegs) are mapped to a set of physical registers (PRegs) by a process called Register Allocation (RA). Once the lifetime of the logical register is completed, i.e., there are no more consumers of the value held in the logical register prior to another value being stored in it, the logical-to-physical register mapping is torn down and the physical register is made available for allocation to another logical register. This process is called Register Reclamation (RR). Register mapping is typically held in a hardware table called the Register Allocation Table (RAT). The un-availability of free physical registers (i.e., physical registers not currently mapped to a logical register) causes all instruction allocation to stall until such a time that a free physical register is available, thereby reducing the performance.
One technique of ensuring higher availability of physical registers is to increase the size of the physical register file (PRF), i.e., the number of PRegs. However, as the size of the PRF increases accesses to the PRF take longer. Thus, the size can only be increased to a point where access time still remains fast (i.e., a single cycle).
An orthogonal technique is to improve the usage of the available physical registers. Specifically, having better register reclamation policies will result in better usage of the existing physical registers and in improved performance. Thus Register Reclamation is a significant determinant of performance in modern computer architectures.
One option for improving Register Reclamation is to build more intelligence into the register allocation and reclamation hardware, i.e., a hardware-only solution. Typically, in hardware-only solutions, register reclamation occurs when the logical register (LReg), which is mapped to a physical register (PReg), gets re-defined, i.e., a new Store (Write) occurs to the logical register. However, this store could execute many instructions after the last use of the value in the logical register. Thus the physical register PReg is unused between the last Load (Read) from LReg and the next Store (Write) to LReg. This sub-optimal usage of registers becomes worse when considered in the context of speculative execution as the Store (Write) which is used by the Register Allocation and Reclamation hardware to free up a PReg from the LReg to which it was mapped has to be non-speculative. Thus, efficacy of such hardware-only solutions is limited.